Regviz

NXP Semiconductors /LPC18xx /ETHERNET /MAC_INTR_MASK

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as MAC_INTR_MASK

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/NXP Semiconductors/LPC18xx/ETHERNET/MAC_INTR_MASK#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0RESERVED 0 (PMTIM)PMTIM 0RESERVED0 (TSIM)TSIM 0RESERVED

Description

Interrupt mask register

Fields

RESERVED

Reserved
PMTIM

PMT Interrupt Mask This bit when set, will disable the assertion of the interrupt signal due to the setting of PMT Interrupt Status bit in Table 561.
RESERVED

Reserved.
TSIM

Timestamp interrupt mask When set, this bit disables the assertion of the interrupt signal because of the setting of Timestamp Interrupt Status bit in Table 561
RESERVED

Reserved.

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data